The present invention relates to an improvement in diagnosis of data processing systems.
It is a common practice in data processing systems that upon detection of an erroneous operation, retrial of the operation in question is executed, and when an error is again detected in the retrial operation, the error is regarded to be ascribable to the presence of a failure is the data processing system, whereby diagnosis is made in order to locate the failure after the system has been shut down or while the system is maintained operative. Of course, even when no failure is detected or located, it is necessary to perform tests for various units of the system for the purpose of maintenance and adjustments.
Heretofore, such diagnosis has been executed by leading out exteriorly from flip-flops of a data processing apparatus and connecting them to an oscilloscope to observe visually the operation of the circuits in concern. Another known diagnosis method resides in that the logic states of certain flip-flops of a processor are read out through corresponding addressing (address designation) from a maintenance panel, and the processor is operated and stopped again to read out again the states of the flip-flops in a repeated manner.
FIG. 1 illustrates a typical example of the hitherto known diagnosis.
The illustrated data processing apparatus comprises plug boards 2a, 2b and 2c installed in a package on a back board 1 and logic circuits implemented in the form of integrated circuit and packed on the plug boards 2a, 2b and 2c.
The back board 1 is constituted by a large scale printed circuit board to which several sheets or several tens of sheets of the plug boards each constituted by a smaller size printed circuit board are electrically connected. Although illustration is made only schematically for the sake of simplification, it will be understood that several tens of semiconductor integrated circuits 3a, 3b (hereinafter referred to as IC) are mounted on each of the plug boards 2. In FIG. 1, reference numeral 4 denotes input terminals of ICs 3a, 3b and numeral 5 designates output terminals. Some of the terminals 4 and 5 of the ICs 3a and 3b are mutually connected through lines 6a and 6b wired on the plug board 2a, while other are connected to terminals 7a, 7b, 7c and 7d provided on the plug board 2a. Each of the ICs 3a, 3b incorporates logic circuits (8a, 8b), (8c, 8d) constituted by a combination of logic gates and a circuit constituted by a combination of flip-flops 9.
In operation, logic signals on a micro-strip line deposited on the back board 1 are inputted to a logic combination circuit 8a of the IC 3a through the micro-strip line 6a formed on the plug board 2a and undergo a first logical processing, the results of which are held by flip-flops 9. The logic signals held in the flip-flops 9 are inputted to a combination circuit 8b in the succeeding cycle to be subjected to a second logical processing. The signals thus obtained are then inputted to a combination circuit incorporated in the IC 3b through the micro-strip line 6b wired on the plug board 2a to undergo a third logical processing, the results of which are held by flip-flops 11. In the next cycle, the logic signals held by the flip-flops 11 are subjected to fourth and fifth logical processings in combination circuits 8d and 8e, and the results are held by flip-flops 12. Then, signals from the flip-flops 12 are sent to the plug board 2b through the micro-strip line on the plug board 2a, a pin 7c and a corresponding line 13 on the back board 1 for similar processing operations.
In this manner, the flip-flops provided in the data processing apparatus serve not only to hold the results obtained from the logical processings executed by logic combination circuits but also perform the function to determine the input conditions to the logic combination circuits. Thus, the logic states of the flip-flops provide critical data for grasping the logical operations taking place in the data processing apparatus.
For this reason, it is indispensably required to check the logic states of the flip-flops in order to confirm the normal operation capability, search the cause for erroneous operation or locate the failure portions for the logical adjustment and maintenance operation.
As a method of observing the states of the flip-flops provided in the data processing apparatus, it is arranged that lines are led out from the flip-flops 9 and 11 to be connected to terminals 7a, 7b, 7c, and 7d of the plug board 2a through associated amplifiers 10a, 10b in order to allow the states of the flip-flops to be observed in terms of signal waveforms. To this end, the terminals 7 are selectively connected to an oscilloscope 14 or a logic tracer for the observation of the signal waveform. This method thus requires the leading-out of the individual flip-flops exteriorly for the visual check.
In current data processing apparatus, there is a tendency to increase the scale of logic package implemented in a plug board or a large scale integrated circuit (LSI) in order to meet the demand for a higher density package in order to attain a higher processing speed as well as to allow expansion of logical operations. On the other hand, in the light of the tendency for miniaturizing the plug board and LSI, the number of signal deriving pins which may be provided in LSI and the plug board is necessarily imposed with restriction, making it impossible to provide a large number of terminals for observation through the oscilloscope or tracer. In other words, restriction is imposed to the number of signals available for the visual observation in spite of an extremely large number of logic functions to be checked.
The fact that the number of the flip-flops the states of which can be actually observed is restricted will of course mean that an accurate diagnosis is rendered difficult because the check for a relatively large number of flip-flops has then to be made by resorting to inference or presumption.
The other hereto known diagnosis method which resides in that the operation of a data processing apparatus to be diagnosed is intermittently operated progressively on a step-by-step base in a repeated manner to thereby read out successively the states of flip-flops in sequence for each stop of the processing operations, as described hereinbefore, does not allow the observation to be effected during the operation of the processor. In other words, although the state of a flip-flop, i.e. whether logic "1" or "0" after a certain operation can be read out, it is impossible to know what kind of variation in the signal waveform took place in the transition from one logic state to the other, thus rendering satisfactory diagnosis impractical.